FIE=0, FSAFE=0, FLVL=0, FAUTO=0
Fault Control Register
FIE | Fault Interrupt Enables 0 (0): FAULTx CPU interrupt requests disabled. 1 (1): FAULTx CPU interrupt requests enabled. |
FSAFE | Fault Safety Mode 0 (0): Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFPINx]. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn). 1 (1): Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL]. |
FAUTO | Automatic Fault Clearing 0 (0): Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the state of FSTS[FFULL]. This is further controlled by FCTRL[FSAFE]. 1 (1): Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFLAGx]. |
FLVL | Fault Level 0 (0): A logic 0 on the fault input indicates a fault condition. 1 (1): A logic 1 on the fault input indicates a fault condition. |